1. Technical Field
The present disclosure relates to a semiconductor device having a fin.
2. Description of the Related Art
As one of the scaling techniques for increasing the density of a semiconductor device, a multi-gate transistor has been suggested. The multi-gate transistor is obtained by forming a semiconductor fin on a substrate and forming a gate on the surface of the semiconductor fin.
The multi-gate transistor can be easily scaled because it uses a three-dimensional (3D) channel. In addition, the current control capability can be improved without the need to increase the gate length of the multi-gate transistor. Moreover, it is possible to effectively suppress a short channel effect (SCE) in which an electric potential of a channel region is affected by a drain voltage.
However, as a logic device becomes more highly integrated, design rules are scaled-down. This increases the effect of contact resistance on the performance of a semiconductor device.